1. Field of the Invention
The present invention relates to a trench structure forming on scribe line regions of a wafer substrate for grounding purpose. The trench structure connects all conductive structures in the scribe line regions for complete channeling and collect excess charge created during IC fabrication to discharge; it is used to reduce device damage due to plasma charging phenomena.
2. Description of the Prior Art
With the development of IC fabrication techniques, critical dimensions of integrated circuits have moved down to about 0.25 .mu.m and diameters of fabricated wafers have ranged up to about 8 inches. Selectivity and uniformity of etching process are undoubtedly crucial factors of device performance. As a result, conventional reactive ion etch (RIE)' owning to its high operating pressure, has gradually being replaced by some advanced methods, such as high density plasma (HDP) etch. HDP is the best suited submicron techniques currently being developed. It has the mechanism not only to provide plasma under fairly low pressure to keep ion-bombarding damage minimal, but also to control plasma density and ion energy separately to maintain good etching uniformity of the large-sized wafer. However, one of the drawbacks of HDP is that excess ions are inevitably produced during the etching process under such high density of plasma. These ions eventually attack the device surface and thus affect the process uniformity.
According to the principle of semiconductor devices, one should realize that the quality of gate oxide is a key factor of device performance. Once charging phenomena appeared near the interface of Si--SiO.sub.2, opposite charges are incidentally induced and gathered along the silicon (substrate) side. The characteristics of the gate are thus changed due to the different electrical environment. The affected characteristics include threshold voltage, breakdown voltage and reliability of the product.
Typical charges found in the oxide layers are as follows: (1) interface trapped charge; (2) fixed oxide charge; (3) mobile ion charge; and (4) oxide trapped charge. Among these charges, the oxide trapped charges, which include the electrons and holes produced primarily by process such as ion implantation and plasma etch, are randomly distributed on the oxide layers.
The divergence of local charge distributions results in the accumulation of most charges on conductors (such as polysilicon and aluminum alloys) with relatively large cross section area or with considerably long line length. As the plasma etching continues, the electrical charge keeps on building up until the capacitance limitation has been reached. This limitation is easily been reached for thin layers such as gate oxide. Once the capacitance no longer holds for the oxide, the current would be discharged throughout the layer and end up with charging damages (so call "antenna effect") of the oxide.
Plasma charging damages are the damages induced by plasma. It is essentially resulted from the antenna effect. An antenna ratio is defined as the ratio of the cross sectional areas or line lengths between a conductor and the gate oxide layer. A conductor with a large antenna ratio represents a huge amount of charge accumulation possible within the conductor and relatively high capacitance conceivable on the gate oxide layer. Therefore the larger the antenna ratio is, the more severe the damages would be. In addition, the longer the etching process is, the more severe the damages would also get. The longer the current passes through, the more defects would be created. In general, antenna effects are grouped by process approaches into area effects and length effects. One example for the area effects is photoresist ashing. During the stripping of photoresist layers, conductors have to be exposed under oxygen (mostly used) plasma and the charges are collected area-wise. The larger the conductor area is, the more charges the conductor would pick up. On the other hand, the length effects can be found in etching of polysilicon and aluminum layers. During the etching process, the surfaces of these conductors are protected by other layers (such as the resist layer). One way to take in the charges is from the lateral of the layers. The longer the layers are, the more charges the conductors would receive and the more damaging the device would be.
To enhance the device quality, the present invention proposes a method that can efficiently reduce the damages of plasma charging.